Simultaneous Multithreading Project

Overview and Impact

Simultaneous multithreading is a processor design that combines hardware multithreading with superscalar processor technology to allow multiple threads to issue instructions each cycle. Unlike other hardware multithreaded architectures (such as the Tera MTA), in which only a single hardware context (i.e., thread) is active on any given cycle, SMT permits all thread contexts to simultaneously compete for and share processor resources. Unlike conventional superscalar processors, which suffer from a lack of per-thread instruction-level parallelism, simultaneous multithreading uses multiple threads to compensate for low single-thread ILP. The performance consequence is significantly higher instruction throughput and program speedups on a variety of workloads that include commercial databases, web servers and scientific applications in both multiprogrammed and parallel environments.

Simultaneous multithreading has already had impact in both the academic and commercial communities. The project has produced numerous papers, most of which have been published in journals or the top, journal-quality architecture conferences, and one of which was the most recent paper selected for the 25th Anniversary Anthology of the International Symposium on Computer Architecture, a competition in which the criteria for acceptance was impact. The SMT project at the University of Washington has also spawned other university projects in simultaneous multithreading. Lastly, several U.S. chip manufacturers (Intel, IBM, Sun and Compaq (when it still supported the Alpha microprocessor line) have designed and manufactured SMT processors for the high-end desktop market. Several startups are also building SMT processors.




Commercial Machines

Related Projects

This page maintained by Susan Eggers
eggers [at] cs [dot] washington [dot] edu