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** [http://www.sandia.gov/~bahendr/papers/MTGL.pdf Software and Algorithms for Graph Queries on Multithreaded Architectures] | ** [http://www.sandia.gov/~bahendr/papers/MTGL.pdf Software and Algorithms for Graph Queries on Multithreaded Architectures] | ||
* Jace Mogill's [[Media:Mogill2010_EMSHybridFPGA.pdf | ''Extended Memory Semantics on Hybrid FPGA-x86 Architectures'']] | * Jace Mogill's [[Media:Mogill2010_EMSHybridFPGA.pdf | ''Extended Memory Semantics on Hybrid FPGA-x86 Architectures'']] | ||
* Mandal, Fowler, and Porterfield's [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5452064&tag=1 Modeling Memory Concurrency for Multi-Socket Multi-Core Systems] | * Mandal, Fowler, and Porterfield's [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5452064&tag=1 "Modeling Memory Concurrency for Multi-Socket Multi-Core Systems"] | ||
Revision as of 22:46, 19 October 2010
SoftXMT Project Overview
The Center for Adaptive Supercomputing Software (CASS) at the Pacific Northwest National Laboratory (PNNL) provides a high-level overview of the SoftXMT project, which is one of fifteen tasks the center supports to advance computational capability for solving large irregular problems via multithreading technologies.
Participating organizations include:
- Pacific Northwest National Laboratory (PNNL)
- University of Washington, Computer Science & Engineering
- Cray Inc.
- Convey Inc.
Meeting info
Mondays, 12:30pm, Allen Center room 674 (except November 15: room 503)
Documents
- Project Description
- Threading Packages
- Cray
- Introduction to Cray XMT (MTA) Programming Model
- Overall Cray XMT Documentation
- Paper on original design: The Tera Computer System
- Convey
- Application Papers
- Jace Mogill's Extended Memory Semantics on Hybrid FPGA-x86 Architectures
- Mandal, Fowler, and Porterfield's "Modeling Memory Concurrency for Multi-Socket Multi-Core Systems"
